The present invention relates to a semiconductor memory device, more particularly to an improvement in a sense amplifier of a DRAM.
In company with a recent increase in an operating speed of a microprocessor, a high speed semiconductor memory has been demanded. The advent of a large capacity semiconductor memory and popularization of a portable gadget has further necessitated low power consumption to be realized. It is effective to reduce a bitline capacitance in order to materialize a higher speed device with lower power consumption and various techniques for the purpose have conventionally been contrived.
As main factors constituting a bitline capacitance, there are named: a bitline capacitance with other wirings (including an adjacent bitline) and a diffusion capacitance in a contact portion of a bitline with a diffusion region (hereinafter referred to as bitline contact). The bitline contact is in a broad sense divided into a contact to a diffusion region of a memory cell transistor and contacts in. a transfer gate, a bitline equalizer, a column gate and a sense amplifier, which constitute a sense amplifier section. Since each of circuits constituting the sense amplifier section has conventionally been constructed by an independent element pattern, a bitline contact has been required to be provided for each circuit.
As described above, since a bitline contact has conventionally provided for each circuit constituting the sense amplifier section, it has been difficult to reduce a bitline capacitance and it is, therefore, hard to realized a device with a high speed and low power consumption.